Show HN: FPGA design acceleration – idiomatic Python to synthesizable Verilog
By spym_ · 2026-06-27 · 2 points · 0 comments
https://holoso.digital
Recently I've been working on a certain embedded system that has an FPGA running EKF and some controls. Coding that in RTL is inefficient at best so I turned to HLS and looked around to see what the industry has to offer. I have a pretty extensive simulation and verification sca…
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